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ARAVIS

ARAVIS

ARAVIS: Reconfigurable asynchronous on-chip integrated architecture

Completed

Project type

FUI 3

Project holder

STMicroelectronics Grenoble

Partners

INRIA Grenoble - Rhône-Alpes, Orange Labs, Leti

Non-members Partners

Thomson, TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture d'ordinateurs

Challenges

In 1965, Intel founder Gordon Moore predicted that the number of transistors that can fit onto a square inch of silicon would double every 18 months. Over the past 40 years, Moore's Law has been proven right. Systems-on-Chip (SoC) are now commonly produced at the 90-nanometer and 65-nanometer scales (with the 45-nanometer SoC just over the horizon). However, the next steps -- producing 32-nanometer and 22-nanometer SoC -- presents problems of a whole new kind arising from the behavior of the semiconductor materials themselves when produced at such small scales. The physical properties of these materials can vary considerably on a single chip of just a few square millimeters, resulting in areas with varied performance levels and even areas that are unusable. Processing architectures must thus be reexamined and adjusted to take into account the constraints introduced by technological dispersion from the design phase.

Objectives

Bring architecture and design solutions to calculation platform problems for embedded systems at the 32-nm and 22-nm scales by combining three Technologies de base: - ST's DSPfacbric coarse-grain structure, which aims to implement several dozen identical data paths on the same System-on-Chip (SoC) and to reconfigure them according to the needs of the application - Techniques based on asynchronous logic (in other words, without a clock) to resolve issues arising from the variability of physical characteristics within each processing node - Advanced automatic techniques for dynamic power and activity management according to oftencontradictory demands such as low voltage and calculation power. Bring architecture and design solutions to calculation platform problems for embedded systems at the 32-nm and 22-nm scales by combining three Technologies de base: - ST's DSPfacbric coarse-grain structure, which aims to implement several dozen identical data paths on the same System-on-Chip (SoC) and to reconfigure them according to the needs of the application - Techniques based on asynchronous logic (in other words, without a clock) to resolve issues arising from the variability of physical characteristics within each processing node - Advanced automatic techniques for dynamic power and activity management according to oftencontradictory demands such as low voltage and calculation power. Bring architecture and design solutions to calculation platform problems for embedded systems at the 32-nm and 22-nm scales by combining three Technologies de base: - ST's DSPfacbric coarse-grain structure, which aims to implement several dozen identical data paths on the same System-on-Chip (SoC) and to reconfigure them according to the needs of the application - Techniques based on asynchronous logic (in other words, without a clock) to resolve issues arising from the variability of physical characteristics within each processing node - Advanced automatic techniques for dynamic power and activity management according to oftencontradictory demands such as low voltage and calculation power.

Projet infos page d'un projet

Budget

9,275 K€

Duration

36 month

Human resources allocated

100 men/year