Within the Hardware R&D team, you will be in charge of doing the ASIC physical implementation of eFPGA architectures for current and next generations. You will be responsible for digital Place & Route and STA of the eFPGA IPs. You will define methodologies and develop automated flows to achieve performance goals under AOCV.
This is a challenging position and an opportunity to work within a highly qualified team. You will get the chance to work on one of the most exciting new semiconductor product and on the most advanced process nodes (from 180nm to 7nm and beyond).

Desired skills and experience

•   At least 5 years of experience in ASIC physical implementation
•   In-depth knowledge of digital EDA tool flows required using Cadence tools
•   Experience at IP level and IP integration at top level
•   Experience on advanced technology nodes, such as 28nm, 16nm, 14nm and below is required
•   Experience with make files and scripting languages such as Tcl, Python and bash
•   DRC/LVS error integration and analysis on P&R EDA tools
•   FPGAs architecture and FPGAs software knowledge is a plus
•   Technical background in RTL design (VHDL, Verilog, SystemVerilog) and/or RTL synthesis is a plus
•   Programming experience in C/C++ or similar language is a plus
•   Good written and spoken English is mandatory

The candidate will work in a dynamic environment and will get to work with teams from different technical areas in which new creative and innovative ideas will be much appreciated.