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ASTEC

ASTEC

Astec: Asynchronous Technology for Low-Power & Secure Embedded Systems

Completed

Project type

FUI 6

Project holder

Tiempo

Non-members Partners

Tracedge, CESTI, TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture d'ordinateurs, Sensaris

Challenges

The Astec project uses asynchronous technology developed by Tiempo IC to design integrated circuits. This technology has numerous advantages over conventional synchronous design systems; for example, it can withstand the sharp fluctuations in PVT (process, voltage, and temperature) seen in new nanometric technologies (<65 nm), it is delay- insensitive, it uses very little energy, it is highly responsive, it can be used to secure embedded systems, and it can be used in variable-voltage power supply systems. Astec is intended for low-power embedded applications --like communication sensor networks, portable medical devices, and RFID identifiers-- that need extremely secure components; examples would include encryption and electronic payment systems. These applications serve high-growth markets that need new technologies to increase systems' energy independence, which offers considerable commercial opportunities for asynchronous components.

Objectives

The Astec project aims to develop a family of asynchronous components (IP), including 16-bit and 32-bit core microcontrollers and generic communication and sensor interfaces that are well suited to low-power embedded systems and secure applications. The first chip will be used to build a prototype of a miniature portable device that can collect and transmit physiological data for medical and sports applications. The second chip will come in two versions (standard and attack-resistant), and will be tested in an application that can measure and compare their performance in terms of security. Astec's asynchronous technology must overcome the following technological hurdles before it can be widely adopted: - Concrete proof and test results are needed to demonstrate the technology's performance in terms of energy use, noise, and security on a limited silicon surface; - Asynchronous components (IP) need to be available; - CAD software needs to be developed for asynchronous technology. The Astec project aims to develop a family of asynchronous components (IP), including 16-bit and 32-bit core microcontrollers and generic communication and sensor interfaces that are well suited to low-power embedded systems and secure applications. The first chip will be used to build a prototype of a miniature portable device that can collect and transmit physiological data for medical and sports applications. The second chip will come in two versions (standard and attack-resistant), and will be tested in an application that can measure and compare their performance in terms of security. Astec's asynchronous technology must overcome the following technological hurdles before it can be widely adopted: - Concrete proof and test results are needed to demonstrate the technology's performance in terms of energy use, noise, and security on a limited silicon surface; - Asynchronous components (IP) need to be available; - CAD software needs to be developed for asynchronous technology. The Astec project aims to develop a family of asynchronous components (IP), including 16-bit and 32-bit core microcontrollers and generic communication and sensor interfaces that are well suited to low-power embedded systems and secure applications. The first chip will be used to build a prototype of a miniature portable device that can collect and transmit physiological data for medical and sports applications. The second chip will come in two versions (standard and attack-resistant), and will be tested in an application that can measure and compare their performance in terms of security. Astec's asynchronous technology must overcome the following technological hurdles before it can be widely adopted: - Concrete proof and test results are needed to demonstrate the technology's performance in terms of energy use, noise, and security on a limited silicon surface; - Asynchronous components (IP) need to be available; - CAD software needs to be developed for asynchronous technology.

Projet infos page d'un projet

Budget

3,509 K€

Duration

36 month

Human resources allocated

27 men/year