You are here



Architectures for high-performance static memory


Project type


Project holder

STMicroelectronics Grenoble


DeFacto Technologies, Dolphin Design, Iroc Technologies

Non-members Partners

G-SCOP - Sciences pour la Conception, l'Optimisation et la Production de Grenoble, TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture d'ordinateurs


Aster leverages Grenoble's world-caliber skills in static random access memory (SRAM), a key technology for systems-on-chip (SoC). The SoC market has been growing at around 16% a year--twice the rate of the semiconductor market as a whole. The Aster project aims to develop content-addressable memory for routers--a very-high-growth market--with applications in multimedia and communications. There is currently no easy way for system engineers to combine the design and testing steps. Aster will solve this problem, opening the door to more robust and reliable chips. This will be especially useful for transportation applications and applications requiring extensive data protection. The project will address the very first steps in the value chain by enabling new SoCs that can eventually serve a wide variety of applications.


The project team will develop CAD software that uses programs and files to represent the technology bricks for next-generation memory. Thanks to the high level of automation, engineers will be able to focus on system-level specifications rather than component details. This should result in less-energy-hungry SRAM chips with even greater resistance than radiation-hardened SRAM. It will also cut costs, since engineers will be able to design smaller chips requiring less silicon, and use self-testing features instead of the testers typically used for production. Aster's innovations will be immediately put to use in industry, and are slated to enhance the product lines of three CAD companies.

Projet infos page d'un projet


7,310 K€


36 month

Human resources allocated

63.5 men/year