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Mixed signal silicon Intellectual Property Yield


Project type

FUI 11

Project holder



Pyxalis, Leti

Non-members Partners

Oasic Design Automation, IMEP-LAHC - Institut de Microélectronique Electromagnétisme et Photonique et le LAboratoire d'Hyperfréquences et de Caractérisation


The Mixipy project will bring together four Grenoble-based small businesses to develop design-for-yield software for microelectronic devices. Circuit engineers will be able to use the software to evaluate and improve production yields for the latest generation of integrated circuits. Once the software has been developed, the four businesses involved in the project will create a joint venture to market it.


Existing production processes for sub-45nm wafers are highly aggressive and result in significant variability, which lowers production yields on several levels: design, layout, and lithography. The circuit design applications currently available are limited in scope and not able to provide a comprehensive approach. Mixipy will resolve this problem by developing innovative software that spans the entire circuit design process and lets engineers test the final yield of their circuits right from the design stage--something never before possible.

Projet infos page d'un projet


4,627 K€


30 month

Human resources allocated

31 men/year