Defacto’s SoC Compiler Live Webinar: “How to Make the SoC Design Assembly a Fully Automated Process”
Today the RTL to GDS flow is fully automated but reaching the optimal RTL is still a challenge. Most of the expected automation is at the front-end pre-synthesis IP or SoC assembly stage, where RTL design files and the related design collaterals such as IP-XACT, UPF and SDC need to be to be managed.
Defacto experts are hosting a LIVE webinar on June 3rd 10-11am PDT in which typical cases such as System Integration, RTL Integration and Power Integration will be presented.
System Integration covers the SoC design assembly process with the full support of IP-XACT standard in full compliance with RTL files. Several automated design “extraction, packaging and reuse” capabilities are part of this process.
RTL Integration helps to build and package a complete SoC at RTL with all the mechanisms to edit the design and deliver a correct-by-construction RTL with the associated views such as SDC and UPF, ready for synthesis.
Power Integration automates the management of power intent descriptions through generation, update, promotion and demotion of UPF files. Power Intent Static Checks and UPF-vs-RTL coherency checks are also provided as part of the power integration process.
In summary during the webinar, attendees will get a clear picture of how SoC Compiler helps to build a cost-effectively and robust flow from system specification to logic synthesis.
Audience: CAD Manager, Architects, CAD Engineer, Designers, Integration teams and Verification teams
1. Chouki Aktouf PhD: Founder, CEO and CTO of Defacto
2. Valentin Boyer: Product Manager at Defacto
3. Arthur Kalsing: Senior Software Engineer at Defacto
This webinar is in partnership with SemiWiki and Defacto.